The present invention relates to a digital data encoding circuit and, in particular, to a synchronously operated, digital state machine circuit for encoding a succession of data bits from a Non-Return-to-Zero (NRZ) format to a Coded Marked Inversion (CMI) format.
In applications relating to the transmission of digital data, for example, across an optical fiber link, the format of the transmitted optical signal is always of concern. This is an important consideration because the decision circuitry in the receiver must be able to extract precise timing information from the incoming optical signal. Three main purposes of timing are to allow the signal to be sampled by the receiver at the time the signal-to-noise ratio is a maximum, to maintain the proper pulse spacing, and to indicate the start and end of each timing interval. In addition, since errors resulting from noise and distortion can occur in the signal detection process, it may be desirable for the optical signal to have an inherent error-detecting capability. These features can be incorporated into the data stream by encoding the signal according to, for example, the CMI format which is a well-known technique.
The CMI format is a two-level line code in which digital data is converted into a pair of data bits. An example of a stream of digital data being converted from the NRZ format to the CMI format is shown in FIG. 5. Specifically, a data bit of "0" is converted into a pair of data bits "0,1", and a data bit of "1" is converted alternately into a pair of data bits "0,0" and "1,1". The pair of data bits "1,0" is, by definition, an illegal combination. The converted pair of data bits (i.e., "0,1", "0,0", or "1,1") is transmitted within the same time frame or data period in which the digital data is applied to the encoding unit.
In general, circuits or transmitters which encode a stream of digital data from the NRZ format to the CMI format are known. For example, U.S. Pat. No. 4,189,621 to Scott describes a device for encoding NRZ data into the CMI format. Scott discloses a circuit providing first, second and third signal channels and an output gating circuit. The first signal channel includes an input connected to receive clock-related pulses and a delay circuit for delaying the clock-related pulses by a predetermined amount of time. The second signal channel includes an input connected to receive the clock-related pulses, an input connected to receive NRZ signals to be encoded in the CMI format, and other logic for deriving from the input NRZ signals a sequence of signals related to Return-to Zero (RZ) signals divided by two. The third signal channel is connected to receive NRZ signals and to derive signals related to these NRZ signals. The output gating circuit is connected to receive the signals from the three signal channels for logically combining the output signals from the second and third signal channels in order to derive a sequence of control signals to be supplied to a clock switching circuit connected to the first signal channel. The delay caused by the delay circuit to the clock-related pulses from the first signal channel relative to the delay of the control signals form the second and third signal channels is approximately plus/minus a quarter clock period. This delay circuit presents a major disadvantage in the Scott circuit. Delay circuits, particularly used for delaying clock signals as in Scott, introduce many uncertainties in digital circuits, and such circuits are considered inferior to a completely synchronous circuit. Moreover, delay circuits and the components within require very precise tolerances and, in general, are more expensive than in synchronous circuits. Accordingly, synchronous designs are preferred.
The device of Scott is further disadvantageous in that no means of minimizing the effects of noise is provided.